In order for field effect devices to be able to handle large currents and voltages it becomes necessary for the active regions of such devices to be significantly larger than those used for their counterparts in more conventional applications involving low power. One structure in which this has been achieved, without adding large amounts to the area that is occupied by the device, has been the trench DMOS (double diffusion metal oxide semiconductor) transistor.
An example of such a device is shown in schematic cross-section in FIG. 1. Layer 1 of N+ material is formed at the lower surface of a silicon wafer. Deep trenches in a criss-cross grid-like pattern are etched in the upper surface of the wafer. The walls of these trenches are lined with a layer of dielectric 2, typically silicon oxide, following which they are filled with polysilicon 3. The latter will serve as the gate electrode while layer 2 will serve as the gate oxide. A source region consisting of N+ silicon 4 is formed on either side of gate oxide 2.
Surrounding source 4, and most of the trench, is a body of P type silicon 6. The space between the body 6 and drain layer 1 comprises N- material 7. The device operates like a normal field effect transistor--no current will flow between source 4 and drain 1 until a positive voltage is applied to gate 3, setting up a field across gate dielectric 2 and resulting in the formation of a conductive channel in the active region pointed to by arrow 8. Once this active region becomes N type, current from source 4 is able to traverse P body 6 and enter region 7. The latter includes a drift field which results in the acceleration of electrons over to drain layer 1.
Since the thickness of P body 6 must be kept relatively small in order to provide an optimum channel length for the active region, the separation between P body 6 and drain region 1 is as shown by arrows 11. However, this arrangement causes the device to break down in the vicinity, of the corner of oxide layer 2 first, when sufficient voltage is applied. Breakdown of this type will reduce the device reliability, is destructive, and is to be avoided at all costs. To overcome this problem, P body 6 is shaped so that a part of it extends downwards in selected places thereby reducing the separation between P body 6 and drain 1 at these locations, symbolized by arrows 12. Under these conditions, PN junction breakdown will occur at the interface between 6 and 7 before the gate oxide layer to can be destroyed.
We note that the full device is made up of a series of individual cells, whose width is defined here by arrows 13, arranged as a continuous linear or two-dimensional array.
The major disadvantage of the design illustrated in FIG. 1 is that the cell pitch can be reduced only slightly because of the lateral diffusion of deep P body 6.
In order to overcome this problem the design shown FIG. 2 has been widely adopted in the art. Cells 21, which we will henceforth refer to as active cells, are similar to the cells seen in FIG. 1. Cell 22, henceforth referred to as a protection cell, is shown at one end of the array. Its main distinguishing difference from the active cells is that its P body 26 extends further into N- region 7 than do the active cells, thereby guaranteeing that breakdown will always occur there.
A plan view of the structure is shown in FIG. 3, FIG. 2 being a cross-section of FIG. 3 taken at 2--2. The protection cell is periodically located within the array. In this case, one of every four cells is a protection cell. FIG. 4 shows the arrangement of FIG. 2 in a two-dimensional array of active cells such as a 41 and including one protection cell 42. This design is widely used in the prior art. Note that the dimensions of the protection cell are the same as those of the active cells. This leads to a cell pitch of about 4.5 microns corresponding to a cell density of about 32 million cells per square inch. The separation 45 between cells is typically about 1 micron. Neither the cell density nor the separation between cells is limited by technological considerations, rather these quantities are determined by the need to make the active cells the same size as the protection cell (whose dimension is limited by the simultaneously formed lateral diffusion distance when P body 26 is vertically driven in), in order not to lose the regular array format.
During a routine search of the prior art no references that solve the problem of increasing the array density in the matter taught by the present invention were uncovered. Several references of interest were, however, encountered. For example, Hsieh et al. (U.S. Pat. No. 5,629,543) provide P+ regions that extend into the drift region while the drain region immediately below it extends upwards. Hsieh et al. (U.S. Pat. No. 5,468,982) avoid breakdown at the intersections between the trenches by not forming the N+ source regions there. Bulucea et al. (U.S. Pat. No. 5,410,170) describe several different cell geometries which make for more efficient operation, and Hsieh et al. (U.S. Pat. No. 5,639,676) describe a process for manufacturing a DMOS array using fewer process steps than the prior art.